Sierra Wireless AirLink FXT Series Especificaciones descargar pdf (Pagina 26)

WA_DEV_FEX20_PTS_004 Rev 001 June 30, 2010 26

Expansion Card Product Technical

Specification

Interfaces

4.4.2. I

C Bus

The I

C interface includes a clock signal (SCL) and a data signal (SDA) which complies with

100Kbit/s–standard interface (standard mode: s-mode).

The I

C bus is always in master mode operation.

The maximum speed transfer is 400Kbit/s (fast mode: f-mode).

For more information on the I

C bus, see document [17] “I2C Bus Specification”, Version 2.0, Philips

Semiconductor 1998.

4.4.2.1. Pin Description

Table 16: I

C Bus Pin Description

Number

Signal

I/O

I/O Type

Reset State

Description

Multiplexed

With

SCL

Open drain

Serial Clock

GPIO26

SDA

I/O

Open drain

Serial Data

GPIO27

Refer to section 4.2 Electrical Information for Digital I/O for open drain, 2V8 and 1V8 voltage

characteristics and reset state definitions.

4.4.2.2. Waveforms

The figure below shows the I

C bus waveforms in master mode configuration.

Figure 6. I

C Timing Diagram (Master)

Table 17: I

C Bus AC Characteristics

Signal

Description

Minimum

Typical

Maximum

Unit

SCL-freq

I²C clock frequency

100

400

KHz

T-start

Hold time START condition

0.6

µs

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 59 60

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